FPGA configuration time and PCIe secification

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MAX II CPLD with PFL inside / QSPI flash / PS mode for EP4CGX22 / Configuration mode only won't fit into EPM240M100C5N.

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I don't use the PFL component, its trivial to write a controller to read from QSPI flash and generate the FPP configuration cycles. Here's some information for previous controllers and tests I've done

http://www.ovro.caltech.edu/~dwh/correlator/pdf/timequest_quad_spi_flash.pdf

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf

I've written a configuration controller to read from QSPI flash and configure a Cyclone IV E in FPP mode. It uses 184 LCs.

Cheers,

Dave