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What is "reset supervisor" delay inside the FPGA?
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Its the logic that implements POR.
If you were to create a design with a RST# signal going into the FPGA, then you would typically use a reset supervisor IC to "debounce" the reset signal, eg., a push button.
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I don't see any straight-forward statment in Handbook, that tells to add tRAMP + tPOR, that is 3ms + 9ms.
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Its a conservative calculation, i.e., if you select MSEL for "Fast" POR, then your power supplies have to meet the tRAMP time, and following that tPOR will occur.
Arguably tRAMP is tPOR(min), so you could just use tPOR(max) = 9ms. However, if you're within 3ms of the 100ms requirement, you're too close, and your system would likely fail in many systems, since even the 100ms value is not a guarantee. Read the references in the PDF link I gave above.
Cheers,
Dave
Honored Contributor
