Error (16058): PLLs that use the x1 clock network and same HSSI channel must be in the same bank

I have a working Arria-V design that incorporates multi-rate SDI I/O (using our own logic, not the Altera IP blocks). The design was originally implemented using Quartus 15.0 however I have recently been attempting to update to newer versions of Quartus and have encountered some issues.

When compiled with Quartus 15.0, I have intermittent data integrity issues with the various DCFIFOs used in the design to bridge streaming video signals across different clock domains due to the embedded "set_false_path" timing constraints in the DCFIFO IP. I updated the design to Quartus 17.1 which supports the lpm_hint “DISABLE_EMBEDDED_TIMING_CONSTRAINT=TRUE” and added the timing constraints recommended by the FIFO IP User Guide. This improved things quite a bit, but I am still seeing data corruption on some units.

I read that the recommended set_max_skew constraint is apparently broken for asynchronous clock groups in Quartus versions up to 20.1 or so and I am now trying to migrate to Quartus 22.1std or 21.1.1. With both of these, when I attempt to compile the design I get the error:

Error (16058): PLLs that use the x1 clock network and drive the same HSSI channel must be placed in the same transceiver bank. PLL "HD_Core_VS4KG2_V1v0_5AGXMA5_pipen1b:top|Tx_PLL_HD_5AGX:Tx_PLL_HD|av_xcvr_plls:tx_pll_hd_5agx_inst|pll[0].pll.cmu_pll.tx_pll" and PLL "HD_Core_VS4KG2_V1v0_5AGXMA5_pipen1b:top|Tx_PLL_SD_5AGX:Tx_PLL_SD|av_xcvr_plls:tx_pll_sd_5agx_inst|pll[0].pll.cmu_pll.tx_pll" use the x1 clock network and drive the same HSSI channel, however the PLLs are not assigned to the same transceiver bank. In the Assignment Editor, change the location assignment of the second specified PLL to location "CHANNELPLL_X132_Y53_N33" so the two PLLs are in the same transceiver bank. 

I have added location constraints and been unable to get past this error. For a sanity check, I went back to the working 17.1 version, pulled the locations for my two Tx PLLs from the chip planner, created location constraints for the two PLLs, and recompiled to make sure everything still worked (it did). I then took the design with location constraints and attempted to build with Quartus 21.1.1 and Quartus 22.1std and I continued to get error 16058.

The only thing I can find about this error is that it apparently was a problem with Quartus 17.1 that was fixed in 18.0: https://www.intel.com/content/www/us/en/support/programmable/articles/000082957.html?wapkw=16058

This doesn't match what I see, as 17.1 is working for me but newer versions are failing.

And recommendations for how to get around this error, or how to properly constrain max. skew across async. clock domains with Quartus 17.1?