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cdsteinkuehler's avatar
cdsteinkuehler
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3 years ago

Error (16058): PLLs that use the x1 clock network and same HSSI channel must be in the same bank

I have a working Arria-V design that incorporates multi-rate SDI I/O (using our own logic, not the Altera IP blocks). The design was originally implemented using Quartus 15.0 however I have recently...
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Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi,


I am able to replicate the issue, your design is compiling in Q18.0 without any errors but giving errors in later versions of Quartus.


I am looking into it.


Thank you

Kshitij Goel