Forum Discussion

cdsteinkuehler's avatar
cdsteinkuehler
Icon for New Contributor rankNew Contributor
3 years ago

Error (16058): PLLs that use the x1 clock network and same HSSI channel must be in the same bank

I have a working Arria-V design that incorporates multi-rate SDI I/O (using our own logic, not the Altera IP blocks). The design was originally implemented using Quartus 15.0 however I have recently...
Configuration
Other Ips
Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi,


Thank you, I am able download the design. Now, I will try to compile it and replicate the issue.


Keep you posted.


Thank you

Kshitij Goel