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cdsteinkuehler's avatar
cdsteinkuehler
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3 years ago

Error (16058): PLLs that use the x1 clock network and same HSSI channel must be in the same bank

I have a working Arria-V design that incorporates multi-rate SDI I/O (using our own logic, not the Altera IP blocks). The design was originally implemented using Quartus 15.0 however I have recently...
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Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi,


I do not received any file, you can share it here. There should not be any problem.


Thank you

Kshitij Goel


  • cdsteinkuehler's avatar
    cdsteinkuehler
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    3 years ago

    This is a commercial design and I cannot post the archive to a public forum. I sent you a private message via the forum, not an email. Please check your forum messages (click the user icon in the upper-right corner and select "Messages") and let me know if you do not see the message. The message appears in my "sent" folder on the forum addressed to your userid (https://community.intel.com/t5/user/viewprofilepage/user-id/213298).