ContributionsMost RecentMost LikesSolutionsRe: dcfifo full broken Hi, As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thank you, Kshitij Goel Re: How to modify "RX EQ" under "Stratix 10 E-Tile PHY" Hi, As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thank you, Kshitij Goel Re: dcfifo full broken Hi, Please go through the FIFO Intel® FPGA IP User Guide Thank you, Kshitij Goel Re: Transceiver Native PHY clock and data width Hi, As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thank you, Kshitij Goel Re: How to modify "RX EQ" under "Stratix 10 E-Tile PHY" Hi, Please refer this link for RX Equalization. 8.4. PMA Receiver Equalization Adaptation Usage Model (intel.com) Thank you, Kshitij Goel Re: dcfifo full broken Hi, Are you using FIFO parameter editor or manually instantiating the FIFO IP? Please ensure that the input and output ports used, and the parameter values assigned are valid for the FIFO Intel® FPGA IP core you instantiate for your target device. If still not resolved, share the Quartus project QAR with the detailed steps to replicate the issue at my end. Thank you, Kshitij Goel Re: Transceiver Native PHY clock and data width Hi, It could be due to 8b/10b encoding. For 32bit, there will be 40bits and 62.5*40 = 2500. Hope it clarifies now. Thank you, Kshitij Goel Re: Cyclone IV altgx simulation glitches Hi, As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thank you, Kshitij Goel Re: Cyclone IV altgx simulation glitches Hi Shawn, These are just simulation artifacts, you can ignore them that will not happen in the hardware. Thank you, Kshitij Goel Re: Cyclone IV altgx simulation glitches Hi, Is this issue resolved? Regards, Kshitij Goel