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alexislms's avatar
alexislms
Icon for Contributor rankContributor
2 years ago

dcfifo full broken

dcfifo #( .intended_device_family ("Agilex"), .lpm_numwords (32), .lpm_showahead ("ON"), .lpm_type ( "dcfifo"), .lpm_width ...
Hdl
Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,


Are you using FIFO parameter editor or manually instantiating the FIFO IP?

Please ensure that the input and output ports used, and the parameter values assigned are valid for the FIFO Intel® FPGA IP core you instantiate for your target device.


If still not resolved, share the Quartus project QAR with the detailed steps to replicate the issue at my end.


Thank you,

Kshitij Goel


  • alexislms's avatar
    alexislms
    Icon for Contributor rankContributor
    2 years ago
    Could you forward the document that explains dcfifo? And tell what's wrong?
    All the parameters seem correct. Modelsim and Quartus don't tell me anything about anything wrong.

    Thank you.