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cdsteinkuehler's avatar
cdsteinkuehler
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3 years ago

Error (16058): PLLs that use the x1 clock network and same HSSI channel must be in the same bank

I have a working Arria-V design that incorporates multi-rate SDI I/O (using our own logic, not the Altera IP blocks). The design was originally implemented using Quartus 15.0 however I have recently...
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Kshitij_Intel's avatar
Kshitij_Intel
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3 years ago

Hi,


Can you please share your project.


I will try to reproduce and resolve the issue.


Thank you

Kshitij Goel


  • cdsteinkuehler's avatar
    cdsteinkuehler
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    3 years ago

    I have sent a Quartus archive file via private message.