EP2C20Q240C8N and giga ethernet

Question

Thank you for your reply.

1- Regarding the input clock frequency “fHSCLK”, from the previous mentioned tables, the lowest value of its maximum is 155.5MHZ. So, the lowest value of the maximum fHSCLK for the device (EP2C20Q240C8N) is 155.5 MHZ. Kindly confirm.

Kindly confirm if it is applicable to use the device (EP2C20Q240C8N) in my design with 125 MHZ taking into consideration that, 150 MHZ will be generated internal the FPGA from the used 125 MHZ).

Reference to “Cyclone II Device Family Data Sheet” page 2–53,which stated that: the Cyclone II devices can transmit and receive data through LVDS signals at a data rate of up to 640 Mbps and 805 Mbps. Can I implement the 1G Ethernet using the “EP2C20Q240C8N” ?

altera_forum · Answer

For Ethernet you need an external PHY with a parallel RGMII or GMII interface. Both can be handled by the Cyclone II.

altera_forum · Answer

Thank you for your reply.

1- Is there any problem to handle the 1Gbps Ethernet using the“EP2C20Q240C8N",

Taking into consideration that the"EP2C20Q240C8N" can transmit and receive data

through LVDS signals at a data rate of up to 640 Mbps and 805 Mbps < 1Gbps?

2- I use the cyclone ii device of the part number "EP2C20Q240C8N". My application needs

frequency of 125MHZ. can the cyclone II “EP2C20 FPGA” support this frequency?

Your reply will be highly appreciated.

Waiting your feedback.

Thanks &BR

altera_forum · Answer

The GMII and RGMII interfaces don't use LVDS. They are single ended and use much lower frequencies on a parrallel bus: 125MBps/pin for GMII and 250MBps/pin (DDR) for RGMII. But those interfaces use a lot of pins, so you should check that you have enough pins for your application.

Your second question can't be answered, it depends a lot on your design. You should compile it in Quartus and use Timequest to check that your timing requirements can be met with your design and the device that you selected.

altera_forum · Answer

Thanks a lot for your co-operation. can i implement 1 Gbps ethernet using “EP2C20 FPGA” external PHY with a parallel RGMII or GMII interface?   BR

altera_forum · Answer

Yes, as I just told you. You should just be careful about the number of pins that you'll need to communicate with the PHY (and find a proper PHY, of course).

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EP2C20Q240C8N and giga ethernet

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