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Altera_Forum
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15 years ago

EP2C20Q240C8N and giga ethernet

Thank you for your reply. 1- Regarding the input clock frequency “fHSCLK”, from the previous mentioned tables, the lowest value of its maximum is 155.5MHZ. So, the lowest value of the max...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks a lot for your co-operation.

can i implement 1 Gbps ethernet using “EP2C20 FPGA” external PHY with a parallel RGMII or GMII interface?

BR