DDR PIN placement error

the error message is pretty helpful in this case. for example, pin U15 is not a legal placement for a DQS pin, or even a DQ pin. you should open the pin planner and take a look at the S pins to know where the legal DQS pins are, and Q for the legal DQ pin locations

you may need to rework your pin out to allow for compatible VCCIO on your DDR banks

Thank you,

but how i rework my pin, it depends on the hardware? i can not choose other pins

It also happened to me. During layout we inadvertently made a few wrong swappings ...

Now the Cyclone IV manual states that the DQS are not used for capture, as there is no DLL circuitry on-board. The ALT-MemPHY uses a dedicated capture clock (that one it phase-shifts to make up for PVT-variations).

I didn't see any special silicon for the DQS/DQ/DM pins, so in theory any IO pin should be able to serve the purpose. Is there a document that reveals the DQ/DQS/DM mysteries, why they are fixed to these 'exact' locations ?

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Is there a document that reveals the DQ/DQS/DM mysteries

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The Cyclone IV pinout files are here:

http://www.altera.com/literature/lit-dp.jsp?category=cyc%204&showspreadsheet=y

They list the DQS etc.

When comparing parts, I use the text version of these files and write Tcl scripts to parse the files.

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why they are fixed to these 'exact' locations ?

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DDR2/3 interfacing requires phase shifting the strobe clock to capture the data. Hence a DQS is grouped with a block of DQ registers.

Cheers,

Dave

Hi Dave,

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DDR2/3 interfacing requires phase shifting the strobe clock to capture the data.

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In Cyclone IV the DQS is not used to capture the DDR2 data. This is stated several times in the Cyclone IV data-sheet. Instead ALT-MemPHY uses a phase-shifted clock from the PLL (that generates all memory clocks) to capture the data. It looks to me that all (most) IO-pins are created equal (DDR-out an OE registers etc. in the IO-cell, DDR-in registers in the logic fabric) so how come the DQ/DQS/DQM-pins are more equal? That is the mystery I'd like to see revealed.

Regards,

Josy

thank you guys,

I will request a new board spin to hw team :s

Another question : have you any recommendation for flash memory pinout?

I use Spansion S29GL512N it dosen't work also :( (you can find the project archive to test flash here)

Hi Josy,

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In Cyclone IV the DQS is not used to capture the DDR2 data. This is stated several times in the Cyclone IV data-sheet. Instead ALT-MemPHY uses a phase-shifted clock from the PLL (that generates all memory clocks) to capture the data.

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Thanks for clarifying that. I am using the Stratix IV devices, and incorrectly assumed the interface was the same on the Cyclone IV devices. I'd had to use the Stratix IV pin assignment tables to try to figure out the assignments for DDR and QDR on the Stratix IV GX Development kit.

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It looks to me that all (most) IO-pins are created equal (DDR-out an OE registers etc. in the IO-cell, DDR-in registers in the logic fabric) so how come the DQ/DQS/DQM-pins are more equal? That is the mystery I'd like to see revealed.

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An interesting mystery indeed. Write a DDR2 interface independently of the Altera IP?

Cheers,

Dave

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Another question : have you any recommendation for flash memory pinout?

I use Spansion S29GL512N it dosen't work also :( (you can find the project archive to test flash here)

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The flash interface can use any compatible I/O pins.

Did you simulate your design with the Spansion flash model, or at least simulate it with a simple memory model and check that you have the read/write timing correct?

I've used the Spansion flash on many boards, without issues. Eg., see the timing on p30

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf

Cheers,

Dave

Hi Dave,

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I am using the Stratix IV devices

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In the more commercial projects we have to do with Cyclone IV and if possible the smaller (cheaper) ones, my customer keeps repeating almost daily ...

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Write a DDR2 interface independently of the Altera IP?

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I'm doing exactly that, as a midnight project though. And I must confess, playing it safe, I stuck to the 'Altera assigned DQS/DQ/DM pins' while developing my PHY. But as I said we swapped a few pins incorrectly and in this project I was going to use the Altera IP (until I got my PHY and Controller tuned) to get the system off the ground. Now my partner-developer is complaining that he has to run a NIOSII Ethernet stack with just the internal memory ...

My Phy and controller are quite small compared to the Altera IP, and are dedicated to driving a single memory chip ( or at maximum a single rank Dimm) only and is targeted at Cyclone devices. (Although the idea should also work for Stratix devices ...)

I'll compare a compilation with some non DQS-DQ pins to the compilation with 'correctly assigned' pins.

Regards,

Josy