DDR PIN placement error

Thank you Dave,

I have the some problem :s

Please find attached project

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Yes but even when i choose only placement for "mem_clk" in DIFFIO_p T8 and

"mem_clk_n" in DIFFIO_n T9 (quartus default placement for DQ, DQS, DM...)

i have the same result

when i chek pin planner:

mem_clk : Y6

mem_clk_n : T10

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It sounds like you did not change the assignments.

When you are in Pin Planner, double-click on the cell that says PIN_Y6, and edit it to change it to PIN_T8. Then change PIN_T10 to PIN_T9. Click save, and place-and-route your design.

Cheers,

Dave

Yes but even when i choose only placement for "mem_clk" in DIFFIO_p T8 and

"mem_clk_n" in DIFFIO_n T9 (quartus default placement for DQ, DQS, DM...)

i have the same result

when i chek pin planner:

mem_clk : Y6

mem_clk_n : T10

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result i have only some critical warning...

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The warnings are telling you what you have done wrong. Consult the pin function tables I posted the link to earlier, and it will tell you what the corresponding differential pair groupings are. The Quartus pin planner device view also shows the pairing.

The warning about device speed grade probably means that the DDR controller was not created with the 'project default device', just go back and regenerate the core.

Cheers,

Dave

Thank you Dave,

I return to the main problem THE DDR :s

I have 2 BANK (3 & 4) exclusively for DDR (2.5v), team hw ask me the placement made by Quartus if i select only the bank 3 and 4.

result i have only some critical warning...

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Warning: Unable to place CK/CKn pair mem_clk and mem_clk_n on a differential pin pair because mem_clk has been assigned to a non-differential pin

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Critical Warning: Memory clock pins mem_clk and mem_clk_n must be placed on DIFFIO p- and n-pins

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when i chek pin planner:

mem_clk : Y6

mem_clk_n : T10

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Critical Warning: ALTMEMPHY IP was generated using a speedgrade of 6, but is being compiled for a speedgrade of 8. Timing analysis may not be valid due to violated timing model assumptions.

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Hi Josy,

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If you keep the controller simple, staying away from the fancy things Altera implements in their HPC II controller, it isn't that complex. And in the end the simple controller outperforms the complex one (time and again).

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I like simple too :)

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It is in VHDL

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Great!

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I'm an old-time AHDL hand and I'm hooked on the internal Quartus II simulator and procrastinating on ModelSim , you will tell me I'm wrong, of course :).

I was contemplating to share it when it was ready (just to show off) but I guess sharing with you would probably get me on the way to ModelSim (even advanced: with models!)

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I'd be happy to create a Modelsim testbench around it. Hey, I'll even throw in a VHDL based Avalon-MM master bus functional model for good measure.

Send me an email off-list when your hardware tests show your controller is working, and I'll take it for a spin in the simulator, and see if it'll work with the LPDDR on the BeMicro-SDK. We can post the final version once its working.

Cheers,

Dave

Hi Dave,

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I've written an SDRAM controller before so figured it wouldn't be too impossible (famous last words ...).

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I too progressed via that route. If you keep the controller simple, staying away from the fancy things Altera implements in their HPC II controller, it isn't that complex. And in the end the simple controller outperforms the complex one (time and again).

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Are you writing your core in Verilog or VHDL?

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It is in VHDL (I try not to touch Veriog -> see http://www.alteraforum.com/forum/showthread.php?t=30879 (http://www.alteraforum.com/forum/showthread.php?t=30879))

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Are you simulating using Modelsim and some Micron memory modules?

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I'm an old-time AHDL hand and I'm hooked on the internal Quartus II simulator and procrastinating on ModelSim , you will tell me I'm wrong, of course :).

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Any chance you'll share your code, or at least your experiences once you get things working?

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I was contemplating to share it when it was ready (just to show off) but I guess sharing with you would probably get me on the way to ModelSim (even advanced: with models!)

Best regards,

Josy

Hi Josy,

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I'm doing exactly that, as a midnight project though. And I must confess, playing it safe, I stuck to the 'Altera assigned DQS/DQ/DM pins' while developing my PHY. But as I said we swapped a few pins incorrectly and in this project I was going to use the Altera IP (until I got my PHY and Controller tuned) to get the system off the ground. Now my partner-developer is complaining that he has to run a NIOSII Ethernet stack with just the internal memory ...

My Phy and controller are quite small compared to the Altera IP, and are dedicated to driving a single memory chip ( or at maximum a single rank Dimm) only and is targeted at Cyclone devices. (Although the idea should also work for Stratix devices ...)

I'll compare a compilation with some non DQS-DQ pins to the compilation with 'correctly assigned' pins.

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I was planning on taking a crack at writing an IP core for the low-power DDR on the BeMicro-SDK kit. I've written an SDRAM controller before so figured it wouldn't be too impossible (famous last words ...).

Are you writing your core in Verilog or VHDL? Are you simulating using Modelsim and some Micron memory modules? Any chance you'll share your code, or at least your experiences once you get things working?

Cheers,

Dave

Hi Dave,

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I am using the Stratix IV devices

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In the more commercial projects we have to do with Cyclone IV and if possible the smaller (cheaper) ones, my customer keeps repeating almost daily ...

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Write a DDR2 interface independently of the Altera IP?

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I'm doing exactly that, as a midnight project though. And I must confess, playing it safe, I stuck to the 'Altera assigned DQS/DQ/DM pins' while developing my PHY. But as I said we swapped a few pins incorrectly and in this project I was going to use the Altera IP (until I got my PHY and Controller tuned) to get the system off the ground. Now my partner-developer is complaining that he has to run a NIOSII Ethernet stack with just the internal memory ...

My Phy and controller are quite small compared to the Altera IP, and are dedicated to driving a single memory chip ( or at maximum a single rank Dimm) only and is targeted at Cyclone devices. (Although the idea should also work for Stratix devices ...)

I'll compare a compilation with some non DQS-DQ pins to the compilation with 'correctly assigned' pins.

Regards,

Josy

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Another question : have you any recommendation for flash memory pinout?

I use Spansion S29GL512N it dosen't work also :( (you can find the project archive to test flash here)

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The flash interface can use any compatible I/O pins.

Did you simulate your design with the Spansion flash model, or at least simulate it with a simple memory model and check that you have the read/write timing correct?

I've used the Spansion flash on many boards, without issues. Eg., see the timing on p30

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf

Cheers,

Dave