DDR PIN placement error

Hi Josy,

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I'm doing exactly that, as a midnight project though. And I must confess, playing it safe, I stuck to the 'Altera assigned DQS/DQ/DM pins' while developing my PHY. But as I said we swapped a few pins incorrectly and in this project I was going to use the Altera IP (until I got my PHY and Controller tuned) to get the system off the ground. Now my partner-developer is complaining that he has to run a NIOSII Ethernet stack with just the internal memory ...

My Phy and controller are quite small compared to the Altera IP, and are dedicated to driving a single memory chip ( or at maximum a single rank Dimm) only and is targeted at Cyclone devices. (Although the idea should also work for Stratix devices ...)

I'll compare a compilation with some non DQS-DQ pins to the compilation with 'correctly assigned' pins.

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I was planning on taking a crack at writing an IP core for the low-power DDR on the BeMicro-SDK kit. I've written an SDRAM controller before so figured it wouldn't be too impossible (famous last words ...).

Are you writing your core in Verilog or VHDL? Are you simulating using Modelsim and some Micron memory modules? Any chance you'll share your code, or at least your experiences once you get things working?

Cheers,

Dave