DDR PIN placement error

Hi Dave,

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I am using the Stratix IV devices

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In the more commercial projects we have to do with Cyclone IV and if possible the smaller (cheaper) ones, my customer keeps repeating almost daily ...

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Write a DDR2 interface independently of the Altera IP?

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I'm doing exactly that, as a midnight project though. And I must confess, playing it safe, I stuck to the 'Altera assigned DQS/DQ/DM pins' while developing my PHY. But as I said we swapped a few pins incorrectly and in this project I was going to use the Altera IP (until I got my PHY and Controller tuned) to get the system off the ground. Now my partner-developer is complaining that he has to run a NIOSII Ethernet stack with just the internal memory ...

My Phy and controller are quite small compared to the Altera IP, and are dedicated to driving a single memory chip ( or at maximum a single rank Dimm) only and is targeted at Cyclone devices. (Although the idea should also work for Stratix devices ...)

I'll compare a compilation with some non DQS-DQ pins to the compilation with 'correctly assigned' pins.

Regards,

Josy