Honored Contributor
Honored ContributorHi Dave,
--- Quote Start --- I've written an SDRAM controller before so figured it wouldn't be too impossible (famous last words ...). --- Quote End --- I too progressed via that route. If you keep the controller simple, staying away from the fancy things Altera implements in their HPC II controller, it isn't that complex. And in the end the simple controller outperforms the complex one (time and again). --- Quote Start --- Are you writing your core in Verilog or VHDL? --- Quote End --- It is in VHDL (I try not to touch Veriog -> see http://www.alteraforum.com/forum/showthread.php?t=30879 (http://www.alteraforum.com/forum/showthread.php?t=30879)) --- Quote Start --- Are you simulating using Modelsim and some Micron memory modules? --- Quote End --- I'm an old-time AHDL hand and I'm hooked on the internal Quartus II simulator and procrastinating on ModelSim , you will tell me I'm wrong, of course :). --- Quote Start --- Any chance you'll share your code, or at least your experiences once you get things working? --- Quote End --- I was contemplating to share it when it was ready (just to show off) but I guess sharing with you would probably get me on the way to ModelSim (even advanced: with models!) Best regards, Josy
