DDR PIN placement error

Thank you Dave,

I return to the main problem THE DDR :s

I have 2 BANK (3 & 4) exclusively for DDR (2.5v), team hw ask me the placement made by Quartus if i select only the bank 3 and 4.

result i have only some critical warning...

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Warning: Unable to place CK/CKn pair mem_clk and mem_clk_n on a differential pin pair because mem_clk has been assigned to a non-differential pin

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Critical Warning: Memory clock pins mem_clk and mem_clk_n must be placed on DIFFIO p- and n-pins

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when i chek pin planner:

mem_clk : Y6

mem_clk_n : T10

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Critical Warning: ALTMEMPHY IP was generated using a speedgrade of 6, but is being compiled for a speedgrade of 8. Timing analysis may not be valid due to violated timing model assumptions.

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