DC offset removal using FPGA?

--- Quote Start ---

the sampling frequency fs used in the FIR filter is the same which would be used by the ADC for sampling?

--- Quote End ---

No, it does not have to be. However, it is much simpler to deal with a system where the two are the same. Unless you have a good reason to do otherwise (eg., ADC clock rate is too fast or really slow), try to keep the clocks the same frequency.

No matter what the clock frequencies of the ADC and FPGA are, you conceptually process the data at the clock rate of the adc, and you design the FIR filter coefficients at the clock rate of the adc.

Cheers,

Dave

--- Quote Start ---

1- How to we decide the tap delay? If i have a signals, at what factor is it dependent?

--- Quote End ---

The tap delay is one sample period.

If your ADC and FPGA use a common clock frequency, then the logic is as drawn in the documents.

If your ADC runs faster than the FPGA, then inside the FPGA, the samples from the ADC will be in parallel, eg. for a 500MHz ADC interfaced to a 250MHz FPGA, the FPGA will have to deal with 2 new ADC samples every clock. The FIR filter logic is essentially reproduced twice for this case.

If your ADC runs slower than the FPGA, then you can implement 'folding' or time-division multiplexing. Basically you can write data to RAM at one clock rate, and read it out at a much faster clock rate, so that you can send the data through a FIR filter (or multiplier-adder) much faster, and reuse DSP blocks (reduce the logic required in the FPGA).

--- Quote Start ---

2- How do i figure out the co-efficients or the multiplication values for the impulse response.

--- Quote End ---

You can use a tool like MATLAB's FDAtool (a filter designer tool). The filter design depends on what you are trying to achieve; are you trying to preserve a band of frequencies, are you trying to correct for a passband response, are you going to be changing the sample rate? I can recommend some books if you like.

--- Quote Start ---

As the filter coefficients in my case are most important as they provide me with the amount of weightage given to each delayed element.

--- Quote End ---

Sorry, I don't follow this comment. You'll need to explain yourself a little clearer.

Cheers,

Dave

ALso please verify:

the sampling frequency fs used in the FIR filter is the same which would be used by the ADC for sampling?

hi, i just went through the slides and studied the handouts for implementations. The thing i am confused is that there are mentioned three things for a digital filter:

-an adder

- a multiplier

- a delay element

these are definitely there due to the impulse responses.

NOTE: i am just studying and talkign about FIR filters at the moment.

I have two questions if someone could clarify:

1- How to we decide the tap delay? If i have a signals, at what factor is it dependent?

2- How do i figure out the co-efficients or the multiplication values for the impulse response.

As the filter coefficients in my case are most important as they provide me with the amount of weightage given to each delayed element.

Please clarigy?

--- Quote Start ---

Thank you for the material, i will look into it in detail and will try doing some matlab testing. I think i will start up with some IIR filter. Will any type of IIR filter work fine?

--- Quote End ---

No, IIR filters will not just work fine.

If you are just starting to learn about filters. Learn about FIR first.

In MATLAB, there are z-transform analysis tools that will help you plot the poles and zeros of IIR filters. These plots must be used to confirm the stability of the quantized filter response. (Don't worry if these words are meaningless to you at the moment - but at least now you know what words to look for.).

Cheers,

Dave

--- Quote Start ---

But if i am right, i need to simulate this model using matlab to atleast figure out the basics of how moving average filter works.

--- Quote End ---

Simulation using MATLAB is a good approach. The slides have an example of a moving average filter, and an FIR filter. The main difference between a moving average filter and a FIR filter is (potentially) a scaling factor.

For example, a 4-point moving average filter is simply the average of 4-samples

y[m] = 1/4*sum_{n=0}{n=3} x[m-n]

whereas a 4-coefficient FIR filter is

y[m] = sum_{n=0}{n=3} h[n]x[m-n]

If h[n] = 1/4, then the two are the same. However, there is really no need to have 1/4 for each coefficient, as they can all be 1, and the final sum can be right-shifted by 2-bits to perform the divide by 4. This essentially gets you back to the moving average equation.

A moving average filter is a pretty simple filter. It might not be appropriate for your application, but it will help you understand filters, so go ahead and simulate it in both MATLAB and Modelsim.

Cheers,

Dave

--- Quote Start ---

why are IIR recommended, can we use FIR too?

--- Quote End ---

Either will work. Ultimately it comes down to filter performance versus FPGA resources; IIRs can be more efficient, but they can have issues with stability and phase non-linearity, however, these issues can be overcome.

--- Quote Start ---

I would be thankful for any help in form of any manuals or tutorials for implementation of these concepts in equivalent verilog (FPGA) domain?

--- Quote End ---

Here's a tutorial you can look at, with associated VHDL

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.zip)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc2011_fpga_dsp_code.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc2011_fpga_dsp_code.zip)

Cheers,

Dave

Also, why are IIR recommended, can we use FIR too?

I would be thankful for any help in form of any manuals or tutorials for implementation of these concepts in equivalent verilog (FPGA) domain?