DC offset removal using FPGA?

hi, i just went through the slides and studied the handouts for implementations. The thing i am confused is that there are mentioned three things for a digital filter:

-an adder

- a multiplier

- a delay element

these are definitely there due to the impulse responses.

NOTE: i am just studying and talkign about FIR filters at the moment.

I have two questions if someone could clarify:

1- How to we decide the tap delay? If i have a signals, at what factor is it dependent?

2- How do i figure out the co-efficients or the multiplication values for the impulse response.

As the filter coefficients in my case are most important as they provide me with the amount of weightage given to each delayed element.

Please clarigy?