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Altera_Forum
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14 years ago

DC offset removal using FPGA?

I am new to interface FPGAs with DSP concepts. I have ADCs and then i have deserializers after them to parallelize the data. So should i apply the DC removal after the deserializer or before it? ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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why are IIR recommended, can we use FIR too?

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Either will work. Ultimately it comes down to filter performance versus FPGA resources; IIRs can be more efficient, but they can have issues with stability and phase non-linearity, however, these issues can be overcome.

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I would be thankful for any help in form of any manuals or tutorials for implementation of these concepts in equivalent verilog (FPGA) domain?

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Here's a tutorial you can look at, with associated VHDL

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.zip)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc2011_fpga_dsp_code.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc2011_fpga_dsp_code.zip)

Cheers,

Dave