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Altera_Forum
Honored Contributor
Honored ContributorDC offset removal using FPGA?
I am new to interface FPGAs with DSP concepts. I have ADCs and then i have deserializers after them to parallelize the data. So should i apply the DC removal after the deserializer or before it? ...
Altera_ForumHonored Contributor
Honored ContributorALso please verify:
the sampling frequency fs used in the FIR filter is the same which would be used by the ADC for sampling?
