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Altera_Forum's avatar
Altera_Forum
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14 years ago

DC offset removal using FPGA?

I am new to interface FPGAs with DSP concepts. I have ADCs and then i have deserializers after them to parallelize the data. So should i apply the DC removal after the deserializer or before it? ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Do u mean that the tap delay which is infact the number of coefficients will be equal to the number of samples we have at the imput?