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1- How to we decide the tap delay? If i have a signals, at what factor is it dependent?
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The tap delay is one sample period.
If your ADC and FPGA use a common clock frequency, then the logic is as drawn in the documents.
If your ADC runs faster than the FPGA, then inside the FPGA, the samples from the ADC will be in parallel, eg. for a 500MHz ADC interfaced to a 250MHz FPGA, the FPGA will have to deal with 2 new ADC samples every clock. The FIR filter logic is essentially reproduced twice for this case.
If your ADC runs slower than the FPGA, then you can implement 'folding' or time-division multiplexing. Basically you can write data to RAM at one clock rate, and read it out at a much faster clock rate, so that you can send the data through a FIR filter (or multiplier-adder) much faster, and reuse DSP blocks (reduce the logic required in the FPGA).
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2- How do i figure out the co-efficients or the multiplication values for the impulse response.
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You can use a tool like MATLAB's FDAtool (a filter designer tool). The filter design depends on what you are trying to achieve; are you trying to preserve a band of frequencies, are you trying to correct for a passband response, are you going to be changing the sample rate? I can recommend some books if you like.
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As the filter coefficients in my case are most important as they provide me with the amount of weightage given to each delayed element.
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Sorry, I don't follow this comment. You'll need to explain yourself a little clearer.
Cheers,
Dave
Honored Contributor
