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the sampling frequency fs used in the FIR filter is the same which would be used by the ADC for sampling?
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No, it does not have to be. However, it is much simpler to deal with a system where the two are the same. Unless you have a good reason to do otherwise (eg., ADC clock rate is too fast or really slow), try to keep the clocks the same frequency.
No matter what the clock frequencies of the ADC and FPGA are, you conceptually process the data
at the clock rate of the adc, and you design the FIR filter coefficients
at the clock rate of the adc.
Cheers,
Dave
Honored Contributor
