Cyclone V PLL outclock is zero

Question

Hi everyone

I use PLL to generate 137Mhz for my Qsys system. The inclock is 125MHz which is from on-board oscillator, but the outclock of PLL is zero, and I don't know why. :(

I build my project on Cyclone V GT FPGA development kit, and I use Quartus 13.1 update 4 Full version.

I use the golden_top example from Altera and then build my project including the Qsys system and the PLL on it.

I have been struggled with this issue for a week and I cannot do anything else till it get solved.

Can someone help me out

altera_forum · Answer

If the PLL doesn't produce anything check the reset signal (and the locked signal). As most designs use synchronous resets make sure that the clock domain where the reset comes from is not the same as the output clock.

altera_forum · Answer

can you be more specific.  I use signalTap and the locked signal is zero, does it mean my PLL has lost lock.

altera_forum · Answer

The locked signal should go high if pll is locked to the reference clock and you are safe to use it.

If it stays low, there is obiously something wrong.

Check the reset signal of that pll. Typically it is high active!

I also would advice you to connect the locked- and reset-signal together with the clock to some pin header and analyse it with an oscilloscope.

altera_forum · Answer

Thanks a lot, supernode.  I have just fixed this problem by alternating 125Mhz clock with 100Mhz clock input of PLL. I think the reason for this issue is that 125Mhz is GPLL-req's External term.

altera_forum · Answer

You must specify the clocks in the megawizard according to your real clock frequency that is going into the PLL. Otherwise the output clocks will have a unwanted frequency or the PLL will not lock.

If you have 125MHz on your board, then set it to 125!

External termination (I think that is what you meant?!) depends on your board design and can be adjusted via the assigments editor (I think Cyclone V devices have internal termination resistors for LVDS inputs).

Not terminating a clock signal may result in unwanted signal distortion. Make sure your PLL sees a quite good incoming clock signal. Measure the clock signal at the FPGAs clock imput pin.

Forum Discussion

Cyclone V PLL outclock is zero

8 Replies

Recent Discussions

Arria 10: Remote Update Factory Fallback won't work & Watchdog does not trigger

Max10 FPGA Programming with .pof file

Agilex 5 RSU, application image addition fails

MAX10 RSU upgrade succeeds, but device boots Factory image instead of Application

Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy