Forum Discussion
Altera_Forum
Honored Contributor
11 years agoCyclone V PLL outclock is zero
Hi everyone I use PLL to generate 137Mhz for my Qsys system. The inclock is 125MHz which is from on-board oscillator, but the outclock of PLL is zero, and I don't know why. :( I build my projec...
Altera_Forum
Honored Contributor
11 years agoI got it, thanks a lot supernode. :D