Forum Discussion
New ContributorHSIO Differential Clock Output VOD and VOCM
Dear Intel Support Team,
We are using the Agilex 5 FPGA A5ED065BB32AI4S in our design.
We plan to use an HSIO differential clock output from the FPGA and connect this output to the differential clock input of an external PLL/clock device.
The FPGA HSIO supply for this interface is currently 1.2 V.
While reviewing the Agilex 5 True Differential Signaling documentation and differential I/O design guidelines, we could not find the complete electrical specifications for the HSIO differential clock output, particularly the following parameters:
- Differential output voltage (VOD) – minimum, typical, and maximum values.
- Output common-mode voltage (VOCM) – minimum, typical, and maximum values.
- Whether these VOD and VOCM values are dependent on the VCCIO/HSIO supply voltage of 1.2 V.
- Whether the specified VOD/VOCM values are applicable when the HSIO output is configured specifically as a clock output for feeding an external PLL/clock input.
- Any recommended termination, AC-coupling, or DC-coupling configuration for this application.
- Please confirm whether there are any restrictions on using the HSIO clock output to directly drive an external differential PLL reference-clock input.
Could you please provide the applicable DC and AC electrical specifications or the relevant datasheet/table for the HSIO differential clock output of the A5ED065BB32AI4S?
We specifically need the VOD and VOCM values to verify electrical compatibility with the external PLL input.
Regards,
Jay Krishna
Hi,
For the FPGA receiver, the key parameters are VID and VICM.
From the schematic, the 10 kΩ/30 kΩ divider biases both inputs to approximately 0.75 × VIO_BANK0 (≈0.9 V for a 1.2 V bank), which falls within the documented True Differential Signaling receiver common-mode range. Therefore, the bias network itself appears compatible with the Agilex 5 HSIO receiver requirements. The remaining check is that the incoming differential clock meets the specified VID range and uses the recommended differential termination.
Regards,
Altera Tech Support
5 Replies
Ash_R_AlteraRegular Contributor
Hi Jay Krishna,
Thank you for the detailed query. Please refer to Table 42 – HSIO Differential I/O Standards Specifications in the Agilex 5 FPGAs and SoCs Device Data Sheet (Doc ID: 813918) for the complete electrical specifications.
Addressing your questions directly:
- VOD and VOCM values — These are tabulated under the True Differential Signaling row in Table 42. The nominal VCCIO_PIO for this standard on Agilex 5 HSIO is 1.3 V, not 1.2 V. Please verify your HSIO supply rail — operating at 1.2 V may place you outside the characterized range.
- Supply dependency — Yes, VOD and VOCM are dependent on VCCIO_PIO. Use the 1.3 V row in Table 42 for correct min/typ/max values.
- Clock output to external PLL — The True Differential Signaling transmitter output on HSIO is suitable for driving an external differential PLL reference input, provided the external PLL's VID input range is compatible with the FPGA's VOD specification from Table 42.
- Termination recommendation — For clock signals driving an external PLL:
- Use AC coupling with 100 nF capacitors on each differential leg if the external device has its own internal common-mode biasing.
- Use DC coupling with a 100 Ω differential termination resistor at the receiver if common-mode levels are matched.
- Avoid DC-coupling without confirming VOCM compatibility between the FPGA output and the PLL input.
5. No restrictions apply to using HSIO as a differential clock output for an external PLL, as long as VCCIO_PIO = 1.3 V and the load termination is correct.
Please confirm your HSIO supply voltage and share the external PLL's differential input specifications so we can verify full electrical compatibility.
Regards,
Altera Tech Support
jaykrishna1Dear Intel Support Team,
Thanks for you reply .We are also using A5ED065BB32AI4S with an external PLL differential clock. The PLL output is AC-coupled through capacitors and then biased using an external bias network before connecting to the FPGA HSIO clock input. The HSIO bank supply is 1.2 V.
VIO_BANK0 is 1.2V.
Please review the attached schematic and confirm:
1.Is this external biasing configuration acceptable for the HSIO clock input?
2.Is the applied common-mode voltage within the allowed range?
Regards,
Jay Krishna- Ash_R_Altera
Hi Jaykrishna,
Thank you for the detailed question.
Based on the Agilex 5 Device Data Sheet, the HSIO True Differential Signaling transmitter is only characterized and supported with VCCIO_PIO = 1.3 V. The datasheet table for HSIO Differential I/O Standards Specifications provides the following transmitter specifications for True Differential Signaling 1.3-V (LVDS-compatible) Tx/Rx: [docs.altera.com]
- VOD: 247 mV (min) to 454 mV (max)
- VOCM: 0.9 V (min), 1.0 V (typ), 1.1 V (max)
- Specifications assume a differential termination of approximately 100 Ω. [docs.altera.com]
For 1.2 V HSIO banks, the datasheet only lists receiver support for the True Differential Signaling standard and does not provide transmitter VOD/VOCM specifications. Therefore, we cannot claim the same VOD/VOCM values for a differential output operating from a 1.2-V HSIO bank. [docs.altera.com]
Looking at the schematic provided, the resistor network (10 kΩ pull-up and 30 kΩ pull-down on each leg) biases the differential pair to approximately 0.75 × VIO_BANK0. For example:
- If VIO_BANK0 = 1.3 V, the bias point is approximately 0.975 V, which is very close to the typical 1.0 V VOCM specified for the 1.3-V True Differential Signaling transmitter.
However, this external bias network does not change the fact that the FPGA output driver characteristics (VOD, VOCM, output swing, etc.) are only characterized for the supported transmitter standard. Therefore, compatibility with the external PLL input should be verified against the FPGA's supported I/O standard and bank voltage configuration.
For driving an external differential PLL reference clock, our recommendation is:
- Use a supported True Differential Signaling (LVDS-compatible) transmitter in a 1.3-V HSIO bank when VOD/VOCM compliance is required.
- Use a 100-Ω differential termination at the receiver as recommended by the differential signaling specification.
- AC-coupling or DC-coupling should follow the PLL vendor's input requirements; the Agilex 5 datasheet does not specify a unique coupling requirement for differential clock outputs. [docs.altera.com]
At present, we are not aware of any additional restriction preventing the use of a supported HSIO differential output as an external PLL reference clock source, provided that the receiving device's common-mode and differential input requirements are met.
Regards,
Altera Tech Support
