HSIO Differential Clock Output VOD and VOCM

Dear Intel Support Team,

We are using the Agilex 5 FPGA A5ED065BB32AI4S in our design.

We plan to use an HSIO differential clock output from the FPGA and connect this output to the differential clock input of an external PLL/clock device.

The FPGA HSIO supply for this interface is currently 1.2 V.

While reviewing the Agilex 5 True Differential Signaling documentation and differential I/O design guidelines, we could not find the complete electrical specifications for the HSIO differential clock output, particularly the following parameters:

1. Differential output voltage (VOD) – minimum, typical, and maximum values.
2. Output common-mode voltage (VOCM) – minimum, typical, and maximum values.
3. Whether these VOD and VOCM values are dependent on the VCCIO/HSIO supply voltage of 1.2 V.
4. Whether the specified VOD/VOCM values are applicable when the HSIO output is configured specifically as a clock output for feeding an external PLL/clock input.
5. Any recommended termination, AC-coupling, or DC-coupling configuration for this application.
6. Please confirm whether there are any restrictions on using the HSIO clock output to directly drive an external differential PLL reference-clock input.

Could you please provide the applicable DC and AC electrical specifications or the relevant datasheet/table for the HSIO differential clock output of the A5ED065BB32AI4S?

We specifically need the VOD and VOCM values to verify electrical compatibility with the external PLL input.

Regards,
Jay Krishna