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jaykrishna1's avatar
jaykrishna1
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25 days ago
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HSIO Differential Clock Output VOD and VOCM

Dear Intel Support Team, We are using the Agilex 5 FPGA A5ED065BB32AI4S in our design. We plan to use an HSIO differential clock output from the FPGA and connect this output to the differential clo...
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  • Ash_R_Altera's avatar
    Ash_R_Altera
    22 days ago

    Hi,

    For the FPGA receiver, the key parameters are VID and VICM.

    From the schematic, the 10 kΩ/30 kΩ divider biases both inputs to approximately 0.75 × VIO_BANK0 (≈0.9 V for a 1.2 V bank), which falls within the documented True Differential Signaling receiver common-mode range. Therefore, the bias network itself appears compatible with the Agilex 5 HSIO receiver requirements. The remaining check is that the incoming differential clock meets the specified VID range and uses the recommended differential termination.

     

    Regards,

    Altera Tech Support

jaykrishna1's avatar
jaykrishna1
Icon for New Contributor rankNew Contributor
23 days ago

Dear Intel Support Team,

Thanks for you reply .We are also using A5ED065BB32AI4S with an external PLL differential clock. The PLL output is AC-coupled through capacitors and then biased using an external bias network before connecting to the FPGA HSIO clock input. The HSIO bank supply is 1.2 V.

VIO_BANK0 is 1.2V.

Please review the attached schematic and confirm:

1.Is this external biasing configuration acceptable for the HSIO clock input?

2.Is the applied common-mode voltage within the allowed range?

Regards,
Jay Krishna

Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
22 days ago

Hi Jaykrishna,

 

Thank you for the detailed question.

Based on the Agilex 5 Device Data Sheet, the HSIO True Differential Signaling transmitter is only characterized and supported with VCCIO_PIO = 1.3 V. The datasheet table for HSIO Differential I/O Standards Specifications provides the following transmitter specifications for True Differential Signaling 1.3-V (LVDS-compatible) Tx/Rx: [docs.altera.com]

  • VOD: 247 mV (min) to 454 mV (max)
  • VOCM: 0.9 V (min), 1.0 V (typ), 1.1 V (max)
  • Specifications assume a differential termination of approximately 100 Ω. [docs.altera.com]

For 1.2 V HSIO banks, the datasheet only lists receiver support for the True Differential Signaling standard and does not provide transmitter VOD/VOCM specifications. Therefore, we cannot claim the same VOD/VOCM values for a differential output operating from a 1.2-V HSIO bank. [docs.altera.com]

Looking at the schematic provided, the resistor network (10 kΩ pull-up and 30 kΩ pull-down on each leg) biases the differential pair to approximately 0.75 × VIO_BANK0. For example:

  • If VIO_BANK0 = 1.3 V, the bias point is approximately 0.975 V, which is very close to the typical 1.0 V VOCM specified for the 1.3-V True Differential Signaling transmitter.

However, this external bias network does not change the fact that the FPGA output driver characteristics (VOD, VOCM, output swing, etc.) are only characterized for the supported transmitter standard. Therefore, compatibility with the external PLL input should be verified against the FPGA's supported I/O standard and bank voltage configuration.

For driving an external differential PLL reference clock, our recommendation is:

  • Use a supported True Differential Signaling (LVDS-compatible) transmitter in a 1.3-V HSIO bank when VOD/VOCM compliance is required.
  • Use a 100-Ω differential termination at the receiver as recommended by the differential signaling specification.
  • AC-coupling or DC-coupling should follow the PLL vendor's input requirements; the Agilex 5 datasheet does not specify a unique coupling requirement for differential clock outputs. [docs.altera.com]

At present, we are not aware of any additional restriction preventing the use of a supported HSIO differential output as an external PLL reference clock source, provided that the receiving device's common-mode and differential input requirements are met.

 

Regards, 

Altera Tech Support

  • jaykrishna1's avatar
    jaykrishna1
    Icon for New Contributor rankNew Contributor
    22 days ago

    Hi,

    Thanks for you reply.

    I understand that the transmitter will work on only TDS 1.3V.

    But now I am asking for the receiver. HSIO bank voltage is 1.2V and using the bank for clock input accordingly please review the bias circuit.

    Thanks 

    Jay 

     

    • Ash_R_Altera's avatar
      Ash_R_Altera
      Icon for Regular Contributor rankRegular Contributor
      22 days ago

      Hi,

      For the FPGA receiver, the key parameters are VID and VICM.

      From the schematic, the 10 kΩ/30 kΩ divider biases both inputs to approximately 0.75 × VIO_BANK0 (≈0.9 V for a 1.2 V bank), which falls within the documented True Differential Signaling receiver common-mode range. Therefore, the bias network itself appears compatible with the Agilex 5 HSIO receiver requirements. The remaining check is that the incoming differential clock meets the specified VID range and uses the recommended differential termination.

       

      Regards,

      Altera Tech Support