HSIO Differential Clock Output VOD and VOCM

Hi Jay Krishna,

Thank you for the detailed query. Please refer to Table 42 – HSIO Differential I/O Standards Specifications in the Agilex 5 FPGAs and SoCs Device Data Sheet (Doc ID: 813918) for the complete electrical specifications.

Addressing your questions directly:

1. VOD and VOCM values — These are tabulated under the True Differential Signaling row in Table 42. The nominal VCCIO_PIO for this standard on Agilex 5 HSIO is 1.3 V, not 1.2 V. Please verify your HSIO supply rail — operating at 1.2 V may place you outside the characterized range.
2. Supply dependency — Yes, VOD and VOCM are dependent on VCCIO_PIO. Use the 1.3 V row in Table 42 for correct min/typ/max values.
3. Clock output to external PLL — The True Differential Signaling transmitter output on HSIO is suitable for driving an external differential PLL reference input, provided the external PLL's VID input range is compatible with the FPGA's VOD specification from Table 42.
4. Termination recommendation — For clock signals driving an external PLL:

• Use AC coupling with 100 nF capacitors on each differential leg if the external device has its own internal common-mode biasing.
• Use DC coupling with a 100 Ω differential termination resistor at the receiver if common-mode levels are matched.
• Avoid DC-coupling without confirming VOCM compatibility between the FPGA output and the PLL input.

       5. No restrictions apply to using HSIO as a differential clock output for an external PLL, as long as VCCIO_PIO = 1.3 V and the load termination is correct.

Please confirm your HSIO supply voltage and share the external PLL's differential input specifications so we can verify full electrical compatibility.

Regards,
Altera Tech Support