Forum Discussion
New ContributorHSIO Differential Clock Output VOD and VOCM
Hi,
For the FPGA receiver, the key parameters are VID and VICM.
From the schematic, the 10 kΩ/30 kΩ divider biases both inputs to approximately 0.75 × VIO_BANK0 (≈0.9 V for a 1.2 V bank), which falls within the documented True Differential Signaling receiver common-mode range. Therefore, the bias network itself appears compatible with the Agilex 5 HSIO receiver requirements. The remaining check is that the incoming differential clock meets the specified VID range and uses the recommended differential termination.
Regards,
Altera Tech Support
New ContributorHi,
Thanks for you reply.
I understand that the transmitter will work on only TDS 1.3V.
But now I am asking for the receiver. HSIO bank voltage is 1.2V and using the bank for clock input accordingly please review the bias circuit.
Thanks
Jay
Regular ContributorHi,
For the FPGA receiver, the key parameters are VID and VICM.
From the schematic, the 10 kΩ/30 kΩ divider biases both inputs to approximately 0.75 × VIO_BANK0 (≈0.9 V for a 1.2 V bank), which falls within the documented True Differential Signaling receiver common-mode range. Therefore, the bias network itself appears compatible with the Agilex 5 HSIO receiver requirements. The remaining check is that the incoming differential clock meets the specified VID range and uses the recommended differential termination.
Regards,
Altera Tech Support
