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Altera_Forum
Honored Contributor
Honored ContributorCyclone V PLL outclock is zero
Hi everyone I use PLL to generate 137Mhz for my Qsys system. The inclock is 125MHz which is from on-board oscillator, but the outclock of PLL is zero, and I don't know why. :( I build my projec...
Altera_ForumHonored Contributor
Honored ContributorWell, I have 125Mhz on board, so the clock set in megawizard is 125Mhz and the output is zero. However, when I use 100Mhz (of course I change the reference clock frequency in Megawizard to 100Mhz too), I got the desired output.
I attached the table of on-board oscillators which I get from reference manual of Cyclone V GT FPGA development kit. Can you find out any thing from this. Thanks in advance. https://www.alteraforum.com/forum/attachment.php?attachmentid=10072 https://www.alteraforum.com/forum/attachment.php?attachmentid=10071 One more thing, what should the Operation mode (in megaWizard) in this situation be? Thanks again
