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Altera_Forum
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11 years ago

Cyclone V PLL outclock is zero

Hi everyone I use PLL to generate 137Mhz for my Qsys system. The inclock is 125MHz which is from on-board oscillator, but the outclock of PLL is zero, and I don't know why. :( I build my projec...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

If the PLL doesn't produce anything check the reset signal (and the locked signal). As most designs use synchronous resets make sure that the clock domain where the reset comes from is not the same as the output clock.