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Honored Contributor
Honored ContributorCyclone V PLL outclock is zero
Hi everyone I use PLL to generate 137Mhz for my Qsys system. The inclock is 125MHz which is from on-board oscillator, but the outclock of PLL is zero, and I don't know why. :( I build my projec...
Altera_ForumHonored Contributor
Honored ContributorIf the PLL doesn't produce anything check the reset signal (and the locked signal). As most designs use synchronous resets make sure that the clock domain where the reset comes from is not the same as the output clock.
