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Altera_Forum
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11 years ago

Cyclone V PLL outclock is zero

Hi everyone I use PLL to generate 137Mhz for my Qsys system. The inclock is 125MHz which is from on-board oscillator, but the outclock of PLL is zero, and I don't know why. :( I build my projec...
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Altera_Forum
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11 years ago

Check if you use the correct clock input (clock pin). As those fpga boards typically have programmable clock buffers check the incoming clock frequency.

Use Normal mode.

Please start reading the documentation of your device. Things like PLL modes are described there in detail.