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Altera_Forum
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11 years ago

Cyclone V PLL outclock is zero

Hi everyone I use PLL to generate 137Mhz for my Qsys system. The inclock is 125MHz which is from on-board oscillator, but the outclock of PLL is zero, and I don't know why. :( I build my projec...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thanks a lot, supernode.

I have just fixed this problem by alternating 125Mhz clock with 100Mhz clock input of PLL. I think the reason for this issue is that 125Mhz is GPLL-req's External term.