Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Cyclone V PLL outclock is zero

Hi everyone I use PLL to generate 137Mhz for my Qsys system. The inclock is 125MHz which is from on-board oscillator, but the outclock of PLL is zero, and I don't know why. :( I build my projec...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

The locked signal should go high if pll is locked to the reference clock and you are safe to use it.

If it stays low, there is obiously something wrong.

Check the reset signal of that pll. Typically it is high active!

I also would advice you to connect the locked- and reset-signal together with the clock to some pin header and analyse it with an oscilloscope.