Cyclone V PLL outclock is zero

You must specify the clocks in the megawizard according to your real clock frequency that is going into the PLL. Otherwise the output clocks will have a unwanted frequency or the PLL will not lock.

If you have 125MHz on your board, then set it to 125!

External termination (I think that is what you meant?!) depends on your board design and can be adjusted via the assigments editor (I think Cyclone V devices have internal termination resistors for LVDS inputs).

Not terminating a clock signal may result in unwanted signal distortion. Make sure your PLL sees a quite good incoming clock signal. Measure the clock signal at the FPGAs clock imput pin.