Forum Discussion
New ContributorAgilex 5 LVDS reciver with custom pins
Hi all,
We are working on an Agilex 5 project based on Eagleboard with the device A5ED065BB32AE4SR0.
Our aim is to use the Cruvi connectors on the board, so we have to configure our pinning according to the board connections. Therefore, we need to use custom pinning for our LVDS receivers.
We have been able to successfully set 4 LVDS lanes in I/O Bank 3B_B lane 1 and the reference clock in a differential pair of the same sub bank but in lane 2.
Then we tried to set a receiver with 8 lanes using the same 4 differential pairs from I/O Bank 3B_B lane1 and 4 available differential pairs from I/O Bank 3B_B lane2. Like in the following pin planner screenshoot
The parameter editor looks like follows, no errors are shown on core generator
Once the LVDS receiver is regenerated and new pins assigned, we got the following error related to the 4 new lanes added:
Error(14566): The Fitter cannot place 4 periphery component(s) due to conflicts with existing constraints (4 I/O pad(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number.
Error(175019): Illegal constraint of I/O pad to the location PIN_K65
Info(14596): Information about the failing component(s):
Info(175028): The I/O pad name(s): Sensor2_Data_n[4]
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(20196): Location(s) already occupied and the components cannot be merged. (1 location affected)
Info(175029): PIN_K65. Already placed at this location: I/O pad Sensor2_Data_p[4](n)
Error(175019): Illegal constraint of I/O pad to the location PIN_K74
Info(14596): Information about the failing component(s):
Info(175028): The I/O pad name(s): Sensor2_Data_n[5]
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(20196): Location(s) already occupied and the components cannot be merged. (1 location affected)
Info(175029): PIN_K74. Already placed at this location: I/O pad Sensor2_Data_p[5](n)
Error(175019): Illegal constraint of I/O pad to the location PIN_T74
Info(14596): Information about the failing component(s):
Info(175028): The I/O pad name(s): Sensor2_Data_n[6]
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(20196): Location(s) already occupied and the components cannot be merged. (1 location affected)
Info(175029): PIN_T74. Already placed at this location: I/O pad Sensor2_Data_p[6](n)
Error(175019): Illegal constraint of I/O pad to the location PIN_T77
Info(14596): Information about the failing component(s):
Info(175028): The I/O pad name(s): Sensor2_Data_n[7]
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(20196): Location(s) already occupied and the components cannot be merged. (1 location affected)
Info(175029): PIN_T77. Already placed at this location: I/O pad Sensor2_Data_p[7](n)
It seems like the fitter tries to create and assign new complementary ping where there are already assigned ones.
Could you help us with this?
Best regards
9 Replies
AqidAyman_AlteraRegular Contributor
Hi,
In the Pin Planner, there is a column where you can see "Differential Pair".
If it is not there, you need to add it manually by customizing the column.
Please ensure every _p pin is matched with its correct _n companion pin.
Regards,
Aqid
K_ED_RD1Hi Aqid,
Thanks for your response.
The differential pair column looks fine as can be seen in the attached image
This is the configuration for the LVDS pins in our QSF file:
set_instance_assignment -name IO_STANDARD "1.2-V TRUE DIFFERENTIAL SIGNALING" -to Sensor2_Data_p[0] -entity Lvds8lanes
set_instance_assignment -name IO_STANDARD "1.2-V TRUE DIFFERENTIAL SIGNALING" -to Sensor2_Data_p[1] -entity Lvds8lanes
set_instance_assignment -name IO_STANDARD "1.2-V TRUE DIFFERENTIAL SIGNALING" -to Sensor2_Data_p[2] -entity Lvds8lanes
set_instance_assignment -name IO_STANDARD "1.2-V TRUE DIFFERENTIAL SIGNALING" -to Sensor2_Data_p[3] -entity Lvds8lanes
set_instance_assignment -name IO_STANDARD "1.2-V TRUE DIFFERENTIAL SIGNALING" -to Sensor2_Data_n[0] -entity Lvds8lanes
set_instance_assignment -name IO_STANDARD "1.2-V TRUE DIFFERENTIAL SIGNALING" -to Sensor2_Data_n[1] -entity Lvds8lanes
set_instance_assignment -name IO_STANDARD "1.2-V TRUE DIFFERENTIAL SIGNALING" -to Sensor2_Data_n[2] -entity Lvds8lanes
set_instance_assignment -name IO_STANDARD "1.2-V TRUE DIFFERENTIAL SIGNALING" -to Sensor2_Data_n[3] -entity Lvds8lanes
set_instance_assignment -name IO_STANDARD "1.2-V TRUE DIFFERENTIAL SIGNALING" -to Sensor2_Data_n[4] -entity Lvds8lanes
set_instance_assignment -name IO_STANDARD "1.2-V TRUE DIFFERENTIAL SIGNALING" -to Sensor2_Data_n[5] -entity Lvds8lanes
set_instance_assignment -name IO_STANDARD "1.2-V TRUE DIFFERENTIAL SIGNALING" -to Sensor2_Data_n[6] -entity Lvds8lanes
set_instance_assignment -name IO_STANDARD "1.2-V TRUE DIFFERENTIAL SIGNALING" -to Sensor2_Data_n[7] -entity Lvds8lanes
set_location_assignment PIN_K77 -to Sensor2_Data_p[0]
set_location_assignment PIN_M77 -to Sensor2_Data_n[0]
set_location_assignment PIN_F77 -to Sensor2_Data_p[1]
set_location_assignment PIN_H77 -to Sensor2_Data_n[1]
set_location_assignment PIN_M67 -to Sensor2_Data_p[2]
set_location_assignment PIN_K67 -to Sensor2_Data_n[2]
set_location_assignment PIN_H67 -to Sensor2_Data_p[3]
set_location_assignment PIN_F67 -to Sensor2_Data_n[3]
set_location_assignment PIN_M65 -to Sensor2_Data_p[4]
set_location_assignment PIN_K65 -to Sensor2_Data_n[4]
set_location_assignment PIN_M74 -to Sensor2_Data_p[5]
set_location_assignment PIN_K74 -to Sensor2_Data_n[5]
set_location_assignment PIN_P74 -to Sensor2_Data_p[6]
set_location_assignment PIN_T74 -to Sensor2_Data_n[6]
set_location_assignment PIN_V77 -to Sensor2_Data_p[7]
set_location_assignment PIN_T77 -to Sensor2_Data_n[7]
FvMSuper Contributor
Hi,
inverted pins of differential pairs are assigned automatically by the fitter, you don't need to enter it in pin planner. Does the error also come up if you only assign p-pins?
- K_ED_RD1
Hi,
As you pointed, leaving the n-pins unassigned seem the fitter associate them automatically to their complementary ones.
However, we are allowed to direclty assingn the n-pins from lane 1 without any issue but not the ones belonging to lane 2 as the following image shows
We would like to know what is the reason why one lane allows direct assign and the other no. Both lanes belong to the same HSIO bank. In the case shown in the image, would all LVDS lanes work properly?
Thanks in advance
- AqidAyman_Altera
Hi,
After you followed the guidelines, are you still observing the issue on the pins in Lane 2 that are not directly assigned to their associated complementary pins?
Regards,
Aqid
- FvM
Hi,
automatically assigned n-pins are obviously wrong. Different bank, no valid LVDS pairs. Can you check if the assignment depends on (possibly wrong) settings in LVDS IP? Otherwise it looks like corrupted Quartus fitter pin table.
Never experienced similar behaviour, however didn't yet work with Agilex LVDS IP.
Regards Frank
- K_ED_RD1
HI Frank,
Thanks for your response.
We have configured the LVDS IP following the guide lines in documentation
The IP pin settings looks like this
No error or warning is shown on IP generator. The IP has been regenerated several times, just in case.
Could you tell us how to check and fix if there is corruption in fitter pin table?
Best regards
