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K_ED_RD1's avatar
K_ED_RD1
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2 months ago

Agilex 5 LVDS reciver with custom pins

Hi all,  We are working on an Agilex 5  project based on Eagleboard with the device A5ED065BB32AE4SR0. Our aim is to use the Cruvi connectors on the board, so we have to configure our pinning accor...
Configuration
Generic Io
Programmable Logic Device
FvM's avatar
FvM
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2 months ago

Hi,

automatically assigned n-pins are obviously wrong. Different bank, no valid LVDS pairs. Can you check if the assignment depends on (possibly wrong) settings in LVDS IP? Otherwise it looks like corrupted Quartus fitter pin table.

Never experienced similar behaviour, however didn't yet work with Agilex LVDS IP.

Regards Frank

K_ED_RD1's avatar
K_ED_RD1
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2 months ago

HI Frank,

Thanks for your response.

We have configured the LVDS IP following the guide lines in documentation

5.1.4. Planning the LVDS SERDES Interface • LVDS SERDES User Guide Agilex™ 5 FPGAs and SoCs • Altera Documentation and Resources Center

The IP pin settings looks like this

 

No error or warning is shown on IP generator. The IP has been regenerated several times, just in case. 

Could you tell us how to check and fix if there is corruption in fitter pin table?

Best regards