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K_ED_RD1's avatar
K_ED_RD1
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2 months ago

Agilex 5 LVDS reciver with custom pins

Hi all,  We are working on an Agilex 5  project based on Eagleboard with the device A5ED065BB32AE4SR0. Our aim is to use the Cruvi connectors on the board, so we have to configure our pinning accor...
Configuration
Generic Io
Programmable Logic Device
K_ED_RD1's avatar
K_ED_RD1
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2 months ago

Hi,

As you pointed, leaving the n-pins unassigned seem the fitter associate them automatically to their complementary ones. 

However, we are allowed to direclty assingn the n-pins from lane 1 without any issue but not the ones belonging to lane 2 as the following image shows

We would like to know what is the reason why one lane allows direct assign and the other no. Both lanes belong to the same HSIO bank. In the case shown in the image, would all LVDS lanes work properly?

Thanks in advance

AqidAyman_Altera's avatar
AqidAyman_Altera
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2 months ago

Hi,

 

After you followed the guidelines, are you still observing the issue on the pins in Lane 2 that are not directly assigned to their associated complementary pins?

 

Regards,

Aqid

  • K_ED_RD1's avatar
    K_ED_RD1
    Icon for New Contributor rankNew Contributor
    2 months ago

    Hi, 

    We have been following the guidelines. The LVDS receiver IP is configured as shown in the initial post, we tried to only assingn the positive pins or both positive ang negative, but it does not work for pins on lane 2.

    Best regards

    • AqidAyman_Altera's avatar
      AqidAyman_Altera
      Icon for Regular Contributor rankRegular Contributor
      2 months ago

      Hi,

       

      Thank you for the confirmation. May I know if you are okay to provide your design file or a simple design where it demonstrate the issue you are facing?

      I would like to reproduce the issue from my side.

       

      Let me know if you wanted to share it privately.

       

      Regards,

      Aqid