Cyclone V issue with Fractional PLL and Reconfig IP Modules

We are using a Cyclone V FPGA with an Altera PLL Reconfig and Fractional PLL IP modules via Quartus 22.1. Appnote AN-661 defines the connection and setup for the two IP blocks, along with the register definitions. Intel design example “pll-reconfig-mnc.qar” is another example file for implementing a Reconfig and fractional PLL, while showing a state machine to write to the Reconfig module. Pretty straight forward material, in which we have implemented nearly identical code to write to the Reconfig module. I have not simulated this, but instead used Signal Tap to show screenshots that match the AN-661(Figure 2) exactly. However I still do not see any change on the 64-bit output when we perform new writes with new PLL settings. I have tried resetting the module before and after the reconfig process per the below comment in the spec, but it made no difference. Also the Intel example did not issue any follow-on resets, but only shows a single programming cycle.

“Altera recommends resynchronizing the fractional PLL using the areset signal if the phase relation‐ ship between output clocks is important. Always assert the areset signal after each mgmt_reset operation or after each fPLL reconfiguration process, to reinitiate the fPLL locking process.”

Here are more notes:

• 64Mhz input clock to the PLL
• “Enable dynamic reconfiguration of PLL” checked in the PLL Megawizard.
• I’m not using any .mif files or implementing this within Platform Designer, but purely in logic (like the Intel example, but with the ability to change the settings later, which we can see during the Signal Tap settings).
• Signal tap shows the Lock de-assert if I reset prior to the Reconfig writes. However regardless of data content with new write data, there is no change on the 64-bit output.
  • In this link, you can see the 64-bit output changing for example.
    • https://www.reddit.com/r/FPGA/s/OLgKNzXb5e
  • Here is a pic of the address, data, and write strobes with lost of setup/hold time and address\data write order the same as the Appnote and the example project. I even tried a delay for the last write to the Start register.

• Here is a pic zoomed out. You can Lock de-assert, but grouping for writes to the Reconfig module (blue demarcation), and then PLL re-assert. There is a change in the data structure of the reconfig_from_pll (63..0) vector just before it locks, but there is no big change in the data for a newly written PLL clock output setting.

• Below is a screen shot from the fit report

Any help is greatly appreciated, as we are stuck. Attached are the .vhd file from the Megawizard for the two IP modules. Please let me know what else I can provide to close this out quickly.

Thanks!