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codecurious
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11 months ago

Cyclone V issue with Fractional PLL and Reconfig IP Modules

We are using a Cyclone V FPGA with an Altera PLL Reconfig and Fractional PLL IP modules via Quartus 22.1. Appnote AN-661 defines the connection and setup for the two IP blocks, along with the registe...
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codecurious's avatar
codecurious
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10 months ago

I need help to close this topic out please (it has been many days working this issue)! I tried the new tool version on the target H/W, and it is still not working. The simulations are working fine now. In Signal Tap I do not see any communication from the PLL. Please help to resolve this.