Forum Discussion
codecurious
New Contributor
New ContributorCyclone V issue with Fractional PLL and Reconfig IP Modules
We are using a Cyclone V FPGA with an Altera PLL Reconfig and Fractional PLL IP modules via Quartus 22.1. Appnote AN-661 defines the connection and setup for the two IP blocks, along with the registe...
AqidAyman_Altera
Regular Contributor
Regular ContributorI have been informed that this case was discussed internally. When changing the counter bit setting from polling mode to waitrequest mode, the issue was resolved.
