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codecurious
New Contributor
New ContributorCyclone V issue with Fractional PLL and Reconfig IP Modules
We are using a Cyclone V FPGA with an Altera PLL Reconfig and Fractional PLL IP modules via Quartus 22.1. Appnote AN-661 defines the connection and setup for the two IP blocks, along with the registe...
EliasBarbudoNew Contributor
New Contributorfrom the first signal tap, it seems like reconfig ip is not sending any data to the PLL, could you double check if the reset of the reconfig ip is not active? the reconfig_to_pll bus should change each time you perform a write operation
