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codecurious
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11 months ago

Cyclone V issue with Fractional PLL and Reconfig IP Modules

We are using a Cyclone V FPGA with an Altera PLL Reconfig and Fractional PLL IP modules via Quartus 22.1. Appnote AN-661 defines the connection and setup for the two IP blocks, along with the registe...
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codecurious's avatar
codecurious
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10 months ago

A couple of notes: 1.) I am able to fully simulate the Reconfig PLL now and my code was functional. I did try to reproduce the Example #1 in the app note 661, but found one thing interesting. In using the exact same value as in the document, I get a frequency of 150.150Mhz vs the 151.11Mhz they mention in the document. I am not sure if you have (or can) verify what frequency you see when using there example project, but I am surprised for such a simple example the frequencies don't match. Let me know what you think.

2.) I am not sure if you found any issues with the build 915 version as mentioned before(?). Let me know if you have. Wednesday I will have access to the H/W and will try the new tool version with hopefully better results. I will keep you posted. Thanks!