Forum Discussion
codecurious
New Contributor
1 year agoCyclone V issue with Fractional PLL and Reconfig IP Modules
We are using a Cyclone V FPGA with an Altera PLL Reconfig and Fractional PLL IP modules via Quartus 22.1. Appnote AN-661 defines the connection and setup for the two IP blocks, along with the registe...
codecurious
New Contributor
1 year agoFirst, thanks so much for your help!! The same active high reset that is connected to the state machine that writes to the Reconfig module is also connected directly to the Reconfig module. I agree I expect to see data changing as in the example of the Reddit link I sent. The instantiation of the Reconfig and PLL IP is pretty straight forward, but unable to get any frequency update/change. Building of the IP and adding it to the project is also pretty straight forward, but I am missing something obviously. I reviewed the log files to see if there was any concerning warnings, but did not see anything (and the fit report shows the instantiation of the IP).