Cyclone V Altera PLL Can't do 100 MHz.

Dear aprado,

Which version of Quartus tool is being used?

Because: in Quartus 13.x all timing constraints are preliminary. From latest Quartus 14.0 this functionality has been finalized.

I have also a question: How you can re-assign FPGA pins at the your PCB design procedure without the usage of FPGA Pin planner. Unfortunately, I observed, that in all latest versions of Quartus (13.0 - 14.0) the Pin planner (Live checker) does not function properly :

"

Live I/O check is currently not supported by the "<name>" family.

(ID: 168014)

http://quartushelp.altera.com/14.0/master.htm#mergedprojects/msgs/msgs/efiochk_live_io_check_not_supported_for_family.htm

"

Regards,

Zsolt

I am using Quartus II 14.0 and I

don't know how to answer your question :(

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Can it be that your misunderstanding the timing report? I guess the problem is that your design can't run at 100 MHz, the PLL shouldn't have problems to generate 100 Mhz (or 200 MHz).

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It could be but when I take out the DMA of the Bridge I have no timing problems, All I have in this bridge (FPGA2SDRAM) is a TSE MAC and a DMA and that's pretty much my whole design...

If the timing report says this FMAX is 91.73 MHz I don't have much to misunderstand, do I?

Thanks

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It's not a PLL problem. You can get detail report about failing pathes in TimeQuest to narrow down the issue.

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I know it's not a PLL per se problem, I think I really made the wrong question. I would like to know the the FPGA2SDRAM / FPGA2HPS LW bridges can run at 100MHz;

I get the top falling path from the SOC System LW Bridge to the HPS System with a slack of -0.4

If fmax is only 91.73 MHz instead of 100 MHz the following things should be investigated:

- .sdc proper timing constraints must be added to this clock pin.

- if PLL has a problem, it is always displayed be the Qsys GUI if configuring the Altera PLL IP ( clock not compensated .... e.g 100 MHz vs. 99.9 MHz)

I think your problem is the first, bad or missing timing constraints.

I suggest to look the following good documentation:

http://www.alterawiki.com/wiki/timequest_user_guide

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It could be but when I take out the DMA of the Bridge I have no timing problems, All I have in this bridge (FPGA2SDRAM) is a TSE MAC and a DMA and that's pretty much my whole design...

If the timing report says this FMAX is 91.73 MHz I don't have much to misunderstand, do I?

Thanks

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I think you have timing constraint problem.

- check .sdc file for the clock signal and add a proper timing constraint

It is not a Altera PLL IP problem (you can check it in Qsys GUI, that all clocks compensated. It it has a problem that means 99.9 Mhz instead of 100 MHz).

I suggest to examine the following good documentation.

http://www.alterawiki.com/wiki/timequest_user_guide

--- Quote Start ---

I know it's not a PLL per se problem, I think I really made the wrong question. I would like to know the the FPGA2SDRAM / FPGA2HPS LW bridges can run at 100MHz;

I get the top falling path from the SOC System LW Bridge to the HPS System with a slack of -0.4

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I have tested all bridges (H2F, F2H, H2F_LW). They can work ~ 100 / 133 / 166 MHz clock frequencies.

I have no information about the FPGA2SDRAM interfaces. (note. this is a interface, not a bridge).

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I have tested all bridges (H2F, F2H, H2F_LW). They can work ~ 100 / 133 / 166 MHz clock frequencies.

I have no information about the FPGA2SDRAM interfaces. (note. this is a interface, not a bridge).

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Thanks for your answer, which FPGA have you used? Did you connect more than one component to the F2H/H2F/H2F_LW bridge? I have the problem when I connect a DMA and the TSE Mac to the F2S bridge.