Cyclone V Altera PLL Can't do 100 MHz.

Dear aprado,

Which version of Quartus tool is being used?

Because: in Quartus 13.x all timing constraints are preliminary. From latest Quartus 14.0 this functionality has been finalized.

I have also a question: How you can re-assign FPGA pins at the your PCB design procedure without the usage of FPGA Pin planner. Unfortunately, I observed, that in all latest versions of Quartus (13.0 - 14.0) the Pin planner (Live checker) does not function properly :

"

Live I/O check is currently not supported by the "<name>" family.

(ID: 168014)

http://quartushelp.altera.com/14.0/master.htm#mergedprojects/msgs/msgs/efiochk_live_io_check_not_supported_for_family.htm

"

Regards,

Zsolt