10CL080YF780I7G BSDL FILE

Hi,

We are currently using your 10CL080YF780I7G in our design.

in the BSDL file, pin F4 is defined as a linkage bit, which prevents us from toggling it through boundary scan.

However, in our design, we are using pin F4 as an output. The design compiles successfully in Quartus without any errors or warnings indicating that this pin should not be used in such a manner.

Could you please clarify why pin F4 is defined as a link bit in the BSDL file?

Is there a recommended workaround or update we should apply to ensure proper JTAG functionality?

.pin file:

BSDL file:

Please note that we have encountered the same problem with the following devices:: 10CL040YF484I7G and 10CL016YF484I7G pin E2 is defined as out bit, while it is IO.

We appreciate your guidance and look forward to your advice.