Forum Discussion
Altera_Forum
Honored Contributor
11 years agoCan it be that your misunderstanding the timing report? I guess the problem is that your design can't run at 100 MHz, the PLL shouldn't have problems to generate 100 Mhz (or 200 MHz).
Can it be that your misunderstanding the timing report? I guess the problem is that your design can't run at 100 MHz, the PLL shouldn't have problems to generate 100 Mhz (or 200 MHz).