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Altera_Forum
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11 years ago

Cyclone V Altera PLL Can't do 100 MHz.

Hello, I am desiging a custom board based on the Altera Cyclone V board. I've changed the board oscillator from 50 MHz to 100 MHz. I am trying to make it go throught a PLL inside QSys and then feed 1...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

If fmax is only 91.73 MHz instead of 100 MHz the following things should be investigated:

- .sdc proper timing constraints must be added to this clock pin.

- if PLL has a problem, it is always displayed be the Qsys GUI if configuring the Altera PLL IP ( clock not compensated .... e.g 100 MHz vs. 99.9 MHz)

I think your problem is the first, bad or missing timing constraints.

I suggest to look the following good documentation:

http://www.alterawiki.com/wiki/timequest_user_guide