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Honored Contributor
Honored ContributorCyclone V Altera PLL Can't do 100 MHz.
Hello, I am desiging a custom board based on the Altera Cyclone V board. I've changed the board oscillator from 50 MHz to 100 MHz. I am trying to make it go throught a PLL inside QSys and then feed 1...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Can it be that your misunderstanding the timing report? I guess the problem is that your design can't run at 100 MHz, the PLL shouldn't have problems to generate 100 Mhz (or 200 MHz). --- Quote End --- It could be but when I take out the DMA of the Bridge I have no timing problems, All I have in this bridge (FPGA2SDRAM) is a TSE MAC and a DMA and that's pretty much my whole design... If the timing report says this FMAX is 91.73 MHz I don't have much to misunderstand, do I? Thanks
