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Altera_Forum
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11 years ago

Cyclone V Altera PLL Can't do 100 MHz.

Hello, I am desiging a custom board based on the Altera Cyclone V board. I've changed the board oscillator from 50 MHz to 100 MHz. I am trying to make it go throught a PLL inside QSys and then feed 1...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Can it be that your misunderstanding the timing report? I guess the problem is that your design can't run at 100 MHz, the PLL shouldn't have problems to generate 100 Mhz (or 200 MHz).

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It could be but when I take out the DMA of the Bridge I have no timing problems, All I have in this bridge (FPGA2SDRAM) is a TSE MAC and a DMA and that's pretty much my whole design...

If the timing report says this FMAX is 91.73 MHz I don't have much to misunderstand, do I?

Thanks